mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 138

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

ColdFire Core
7.2.8
The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control
bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are
accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor
or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access
when in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after reset and
before any compare (CMP), Bcc, or Scc instructions execute.
7-8
Field
BWD
Field
24–0
FSD
Reset
BDM: Load: 0xEE (SR)
27
26
25
15
14
13
T
S
W
R
Store: 0xCE (SR)
Buffered write disable. The ColdFire core is capable of marking processor memory writes as bufferable or
non-bufferable.
0 Writes are buffered and the bus cycle is terminated immediately with zero wait states.
1 Disable the buffering of writes. In this configuration, the write transfer is terminated based on the response time
Note: If buffered writes are enabled (BWD = 0), any error status is lost as the immediate termination of the data
Reserved, must be cleared.
Flash speculation disabled. Disables certain performance-enhancing features related to address speculation in the
flash memory controller.
0 The flash controller tries to speculate on read accesses to improve processor performance by minimizing the
exposed flash memory access time. Recall the basic flash access time is two processor cycles.
1 Certain flash address speculation is disabled.
Reserved, must be cleared.
Trace enable. When set, the processor performs a trace exception after every instruction.
Reserved, must be cleared.
Supervisor/user state.
0 User mode
1 Supervisor mode
15
T
0
of the addressed destination memory device.
Status Register (SR)
transfer assumes an error-free completion.
14
0
0
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
13
S
1
System Byte
Table 7-3. CPUCR Field Descriptions (continued)
12
M
0
11
0
0
Table 7-4. SR Field Descriptions
Figure 7-9. Status Register (SR)
10
1
1
9
I
Description
Description
1
8
0
0
7
0
0
6
Condition Code Register (CCR)
0
0
5
—
X
4
Access: Supervisor read/write
—
N
3
Freescale Semiconductor
—
Z
2
BDM read/write
—
V
1
—
C
0