mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 526

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Version 1 ColdFire Debug (CF1_DEBUG)
Figure 22-18
to the target MCU, there is a 0–1 cycle delay from the host-generated falling edge on BKGD to the
perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the
target to recognize it (at least two target BDC cycles). The host must release the low drive before the target
MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. The
host should sample the bit level about 10 cycles after it started the bit time.
Figure 22-19
to the target MCU, there is a 0–1 cycle delay from the host-generated falling edge on BKGD to the start
of the bit time as perceived by the target MCU. The host initiates the bit time, but the target MCU finishes
it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 BDC clock
cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 cycles
after starting the bit time.
22-34
PERCEIVED START
SPEEDUP PULSE
(TARGET MCU)
TARGET MCU
TO BKGD PIN
HOST DRIVE
OF BIT TIME
BDC CLOCK
BKGD PIN
shows the host receiving a logic 1 from the target MCU. Because the host is asynchronous
shows the host receiving a logic 0 from the target MCU. Because the host is asynchronous
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 22-18. BDC Target-to-Host Serial Bit Timing (Logic 1)
HIGH-IMPEDANCE
R-C RISE
HOST SAMPLES BKGD PIN
10 CYCLES
10 CYCLES
HIGH-IMPEDANCE
HIGH-IMPEDANCE
EARLIEST START
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