mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 554

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Version 1 ColdFire Debug (CF1_DEBUG)
22-62
0x0C–0x0F Indicates the number of address bytes to be loaded into the PST trace buffer. The capturing of branch
0x08–0x0B Indicates the number of data bytes to be loaded into the PST trace buffer. The capturing of peripheral
0x10–0x11 Reserved
PST[4:0]
0x1C
0x1D
0x1A
0x1B
0x1E
0x1F
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
Table 22-27. CF1 Debug Processor Status Encodings with VBus Disabled (continued)
bus data references is controlled by CSR[DDC].
0x08 Begin 1-byte data transfer on DDATA
0x09 Begin 2-byte data transfer on DDATA
0x0A Reserved
0x0B Begin 4-byte data transfer on DDATA
target addresses is controlled by CSR[BTB].
0x0C Reserved
0x0D Begin 2-byte address transfer on DDATA (Displayed address is shifted right 1: ADDR[16:1])
0x0E Begin 3-byte address transfer on DDATA (Displayed address is shifted right 1: ADDR[23:1])
0x0F Reserved
Completed execution of 2 sequential instructions
Completed execution of 3 sequential instructions
Completed execution of 4 sequential instructions
Completed execution of 5 sequential instructions
Completed execution of 6 sequential instructions
Completed execution of 7 sequential instructions
Completed execution of 8 sequential instructions
Completed execution of 9 sequential instructions
Completed execution of 10 sequential instructions
This value signals there has been a change in the breakpoint trigger state machine. It appears as a
single marker for each state change and is immediately followed by a DDATA value signaling the new
breakpoint trigger state encoding.
The DDATA breakpoint trigger state value is defined as (0x20 + 2 × CSR[BSTAT]):
0x20 No breakpoints enabled
0x22 Waiting for a level-1 breakpoint
0x24 Level-1 breakpoint triggered
0x2A Waiting for a level-2 breakpoint
0x2C Level-2 breakpoint triggered
Exception processing. This value signals the processor has encountered an exception condition.
Although this is a multi-cycle mode, there are only two PST = 0x1C values recorded before the mode
value is suppressed.
Emulator mode exception processing. This value signals the processor has encountered a debug
interrupt or a properly-configured trace exception. Although this is a multi-cycle mode, there are only
two PST = 0x1D values recorded before the mode value is suppressed.
Processor is stopped. This value signals the processor has executed a STOP instruction. Although this
is a multi-cycle mode because the ColdFire processor remains stopped until an interrupt or reset
occurs, there are only two PST = 0x1E values recorded before the mode value is suppressed
Processor is halted. This value signals the processor has been halted. Although this is a multi-cycle
mode because the ColdFire processor remains halted until a BDM go command is received or reset
occurs, there are only two PST = 0x1F values recorded before the mode value is suppressed
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Definition
Freescale Semiconductor
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