mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 381

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
PLL Engaged
External (PEE)
PLL Bypassed
External (PBE)
Bypassed Low
Power Internal
(BLPI)
Bypassed Low
Power External
(BLPE)
Mode
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 00
• MCGC1[RDIV] is programmed
• PLLS = 1
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 10
• MCGC1[RDIV] is programmed
• MCGC2[LP] = 0
• MCGC3[PLLS] = 1
• MCGC1[IREFS] = 1
• MCGC1[CLKS] =
• MCGC2[LP] = 1 (and the BDM
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 10
• MCGC2[LP] = 1 (and the BDM
to divide the reference clock to
be within the range of 1 to
2 MHz.
to divide the reference clock to
be within the range of 1 to
2 MHz.
01MCGC3[PLLS] = 0
is disabled)
is disabled)
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Related field values
Table 16-11. MCG Modes of Operation (continued)
MCGOUT is derived from the PLL clock, which is controlled by the
external reference clock. The external reference clock that is enabled
can be produced by an external crystal, ceramic resonator, or another
external clock source connected to the required crystal oscillator
(XOSC). The PLL clock frequency locks to a multiplication factor, as
specified by MCGC3[VDIV], times the external reference frequency, as
specified by MCGC1[RDIV], MCGC2[RANGE], and MCGC3[DIV32]. If
the BDM is enabled, MCGLCLK is derived from the DCO (open-loop
mode) divided by two. If the BDM is not enabled, the FLL is disabled in a
low-power state.
In this mode, MCGT[DRST] is read as a 0 regardless of the value of
MCGT[DRS].
MCGOUT is derived from the external reference clock; the PLL is
operational, but its output clock is not used. This mode is useful to allow
the PLL to acquire its target frequency while MCGOUT is driven from the
external reference clock.
MCGOUT is derived from the external reference clock. The external
reference clock that is enabled can be produced by an external crystal,
ceramic resonator, or another external clock source connected to the
required crystal oscillator (XOSC). The PLL clock frequency locks to a
multiplication factor, as specified by MCGC3[VDIV], times the external
reference frequency, as specified by MCGC1[RDIV], MCGC2[RANGE],
and MCGC3[DIV32]. If the BDM is enabled, MCGLCLK is derived from
the DCO (open-loop mode) divided by two. If the BDM is not enabled, the
FLL is disabled in a low-power state.
In this mode, MCGT[DRST] is read as a 0 regardless of the value of
MCGT[DRS].
MCGOUT is derived from the internal reference clock.
The PLL and FLL are disabled, and MCGLCLK is not available for BDC
communications. If the BDM becomes enabled, the mode switches to
FLL bypassed internal (FBI) mode.
In this mode, MCGT[DRST] is read as a 0 regardless of the value of
MCGT[DRS].
MCGOUT is derived from the external reference clock. The external
reference clock that is enabled can be produced by an external crystal,
ceramic resonator, or another external clock source connected to the
required crystal oscillator (XOSC).
The PLL and FLL are disabled, and MCGLCLK is not available for BDC
communications. If the BDM becomes enabled, the mode switches to
one of the bypassed external modes as determined by the state of
MCGC3[PLLS].
In this mode, MCGT[DRST] is read as a 0 regardless of the value of
MCGT[DRS].
Description
Multipurpose Clock Generator (MCGV3)
16-13