mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 496

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

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Version 1 ColdFire Debug (CF1_DEBUG)
22.1.3
V1 ColdFire devices typically implement a number of modes of operation, including run, wait, and stop
modes. Additionally, the operation of the core’s debug module is highly dependent on a number of chip
configurations which determine its operating state.
When operating in secure mode, as defined by a 2-bit field in the flash memory examined at reset, BDM
access to debug resources is extremely restricted. It is possible to tell that the device has been secured, and
to clear security, which involves mass erasing the on-chip flash memory. No other debug access is allowed.
Secure mode can be used in conjunction with each of the wait and stop low-power modes.
If the BDM interface is not enabled, access to the debug resources is limited in the same manner as a secure
device.
If the device is not secure and the BDM interface is enabled (XCSR[ENBDM] is set), the device is
operating in debug mode and additional resources are available via the BDM interface. In this mode, the
status of the processor (running, stopped, or halted) determines which BDM commands may be used.
Debug mode functions are managed through the background debug controller (BDC) in the Version 1
ColdFire core. The BDC provides the means for analyzing MCU operation during software development.
BDM commands can be classified into three types as shown in
For more information on these three BDM command classifications, see
Command Set Summary.”
The core’s halt mode is entered in a number of ways:
22-4
Command Type
Always-available
Non-intrusive
•
•
•
•
•
•
The BKGD pin is low during POR
The BKGD pin is low immediately after a BDM-initiated force reset (see CSR2[BDFR] in
Section 22.3.3, “Configuration/Status Register 2 (CSR2),”
A background debug force reset occurs (CSR2[BDFR] is set) and CSR2[BFHBR] is set
A computer operating properly reset occurs and CSR2[COPHR] is set
An illegal operand reset occurs and CSR2[IOPHR] is set
An illegal address reset occurs and CSR2[IADHR] is set
Modes of Operations
Secure or
Unsecure
Unsecure
Unsecure
Secure?
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Flash
Enabled or
Disabled
Enabled
Enabled
BDM?
Table 22-2. BDM Command Types
Core Status
Run, Halt
Halt
—
• Read/write access to XCSR[31–24], CSR2[31–24],
• Memory access
• Memory access with status
• Debug register access
• BACKGROUND
• Read or write CPU registers (also available in stop mode)
• Single-step the application
• Exit halt mode to return to the application program (GO)
CSR3[31–24]
Table
for details)
22-2.
Section 22.4.1.5, “BDM
Command Set
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