mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 482

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Timer/PWM Module (TPMV3)
When BDM is active, the timer counter is frozen (this is the value you read). The coherency mechanism
is frozen so the buffer latches remain in the state they were in when the BDM became active, even if one
or both counter halves are read while BDM is active. This assures that if you were in the middle of reading
a 16-bit register when BDM became active, it reads the appropriate value from the other half of the 16-bit
value after returning to normal execution.
In BDM mode, writing any value to TPMxSC, TPMxCNTH, or TPMxCNTL registers resets the read
coherency mechanism of the TPMxCNTH:TPMxCNTL registers, regardless of the data involved in the
write.
21.3.3
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock, and
the overflow flag (TOF) becomes set. Writing to TPMxMODH or TPMxMODL inhibits the TOF bit and
overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000
that results in a free running timer counter (modulo disabled).
Writes to any of the registers TPMxMODH and TPMxMODL actually writes to buffer registers and the
registers are updated with the value of their write buffer according to the value of CLKSB:CLKSA bits:
The latching mechanism is manually reset by writing to the TPMxSC address (whether BDM is active or
not).
When BDM is active, the coherency mechanism is frozen (unless reset by writing to TPMxSC register) so
the buffer latches remain in the state they were in when the BDM became active, even if one or both halves
of the modulo register are written while BDM is active. Any write to the modulo registers bypasses the
buffer latches and directly writes to the modulo register while BDM is active.
21-10
Reset
Reset
•
•
W
W
R
R
If CLKSB and CLKSA are cleared, the registers are updated when the second byte is written
If CLKSB and CLKSA are not cleared, the registers are updated after both bytes were written, and
the TPM counter changes from (TPMxMODH:TPMxMODL – 1) to
(TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made
when the TPM counter changes from 0xFFFE to 0xFFFF
TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)
0
0
7
7
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 21-9. TPM Counter Modulo Register High (TPMxMODH)
0
0
6
6
Figure 21-8. TPM Counter Register Low (TPMxCNTL)
Any write to TPMxCNTL clears the 16-bit counter
5
0
5
0
TPMxMOD[15:8]
0
0
4
4
TPMxCNT[7:0]
0
0
3
3
0
0
2
2
Freescale Semiconductor
0
0
1
1
0
0
0
0