mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 442

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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16-Bit Serial Peripheral Interface (SPI16)
20.1.1
The SPI includes these distinctive features:
20.1.2
The SPI functions in three modes, run, wait, and stop.
The SPI is completely disabled in all other stop modes. When the CPU wakes from these stop modes, all
SPI register content will be reset.
This is a high level description only, detailed descriptions of operating modes are contained in section
Section 20.4.10, “Low Power Mode
20-2
Master mode or slave mode operation
Full-duplex or single-wire bidirectional mode
Programmable transmit bit rate
Double-buffered transmit and receive data register
Serial clock phase and polarity options
Slave select output
Mode fault error flag with CPU interrupt capability
Control of SPI operation during wait mode
Selectable MSB-first or LSB-first shifting
Programmable 8- or 16-bit data transmission length
Receive data buffer hardware match feature
64bit FIFO mode for high speed/large amounts of data transfers.
Run Mode
This is the basic mode of operation.
Wait Mode
SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit
located in the SPIxC2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in
Run Mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI
clock generation turned off. If the SPI is configured as a master, any transmission in progress stops,
but is resumed after CPU goes into Run Mode. If the SPI is configured as a slave, reception and
transmission of a byte continues, so that the slave stays synchronized to the master.
Stop Mode
The SPI is inactive in stop3/stop4 mode for reduced power consumption. If the SPI is configured
as a master, any transmission in progress stops, but is resumed after the CPU goes into Run Mode.
If the SPI is configured as a slave, reception and transmission of a data continues, so that the slave
stays synchronized to the master.
Features
Modes of Operation
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Options.”
Freescale Semiconductor

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