mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 24

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Device Overview
1.4.2
Table 1-5
1.4.3
The multi-purpose clock generator (MCG) module provides several clock source choices for the MCU.
The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL) that are controllable
by an internal or an external reference clock. This module can select either the FLL or PLL clock outputs,
or either the internal or external reference clocks as a source for the MCU system clock.
1-8
OSCOUT
MCGOUT
MCGLCLK
MCGERCLK
MCGIRCLK
MCGFFCLK
LPOCLK
TPMCLK
FTMnCLK
ADACK
Clock
describes each of the system clocks.
System Clocks
Multi-Purpose Clock Generator (MCG)
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
This is the direct output of the external oscillator module and can be selected as the real-time
interrupt (RTI) clock source.
This clock source is used as the CPU clock and is divided by two to generate the peripheral bus
clock. Control bits in the MCG control registers determine which of three clock sources is connected:
This clock drives the CPU, debug, RAM, RGPIO and BDM directly and is divided by two to clock all
peripherals (BUSCLK).
The FTM modules can select MCGOUT as their clock input.
See
clock.
This clock source is derived from the 10/20 MHz DCO (digitally controlled oscillator) or the
20/50 MHz phase-locked loop (PLL) of the MCG when configured to run off of the internal or external
reference clock. Development tools can select this internal self-clocked source (~10 MHz) to speed
up BDC communications in systems where the bus clock is slow.
MCG External Reference Clock — This is the external reference clock and can be selected as the
alternate clock for the ADC and CAN modules.
MCG Internal Reference Clock—This is the internal reference clock and this clock signal is not used
outside of the MSG.
MCG Fixed-Frequency Clock — This generates the fixed frequency clock (FFCLK) after being
synchronized to the bus clock. It can be selected as clock source for the TPM and FTM modules.
The frequency of the FFCLK is determined by the settings of the MCG.
Low-Power Oscillator Clock — This clock is generated from an internal low-power oscillator that is
completely independent of the MCG module. The LPOCLK can be selected as the clock source to
the COP and RTI.
TPM Clock — An optional external clock source for the FTMs and TPM3. This clock must be limited
to one-quarter the frequency of the bus clock for synchronization. Refer to the SOPT2[TPMCCFG]
bit description in
with the FTMs.
FTM Clock — An optional external clock source for the FTMs. This clock must be limited to
one-quarter the frequency of the bus clock for synchronization.
The ADC module also has an internally generated asynchronous clock which allows it to run in
STOP mode (ADACK). This signal is not available externally.
• Internal reference clock
• External reference clock
• Frequency-locked loop (FLL) or phase-locked loop (PLL) output
Chapter 16, “Multipurpose Clock Generator
Section 5.9.9, “System Options 2 (SOPT2)
Table 1-5. System Clocks
Description
(MCGV3)” for details on configuring the MCGOUT
Register,” for details on using TPMCLK
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