mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 407

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

The square-wave output frequency was measured and the relative performance results are presented in
Table
defined as f MHz. The performance of the BCHG loop operating on a GPIO output is selected as the
reference.
17.6.2
In this second example, a 16-bit message is transmitted using three programmable output pins. The output
pins include a serial clock, an active-high chip select, and the serial data bit. The software is configured to
sample the serial data bit at the rising-edge of the clock with the data sent in a most-significant to
least-significant bit order. The resulting 3-bit output is shown in
For this example, the processing of the SPI message is considerably more complex than the generation of
a simple square wave of the previous example. The code snippet used to extract the data bit from the
message and build the required GPIO data register writes is shown in
# subtest: send a 16-bit message via a SPI interface using a RGPIO
Freescale Semiconductor
•
17-11. The relative performance is stated as a fraction of the processor’s operating frequency,
A pulse counter is decremented until the appropriate number of square-wave pulses have been
generated.
SET+CLR_LOOP — For this construct, two store instructions are executed: one to set the GPIO
data pin and another to clear it. Single-cycle NOP instructions (the tpf opcode) are included to
maintain the 50% duty cycle of the generated square wave. The pulse counter is decremented until
the appropriate number of square-wave pulse have been generated.
set+clr (+toggle) (1/12) × f MHz
gpio_data
gpio_clk
gpio_cs
Application 2: 16-bit Message Transmission using SPI Protocol
Loop
bchg
The square-wave frequency is measured from rising-edge to rising-edge,
where the output wave has a 50% duty cycle.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
(1/24) × f MHz
Frequency
# the SPI protocol uses a 3-bit value: clock, chip-select, data
# the data is centered around the rising-edge of the clock
Sq-Wave
Peripheral Bus-mapped GPIO
Figure 17-8. GPIO SPI Example Timing Diagram
Table 17-11. Square-Wave Output Performance
align
CPU f = 50 MHz
Frequency @
2.083 MHz
4.167 MHz
15
16
NOTE
14
Relative
Speed
1.00x
2.00x
13
(1/14) × f MHz
(1/8) × f MHz
Frequency
Sq-Wave
Figure
2
Figure
17-8.
CPU f = 50 MHz
Frequency @
RGPIO
3.571 MHz
6.250 MHz
17-9.
1
0
Rapid GPIO (RGPIO)
Relative
Speed
1.71x
3.00x
17-9