mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 522

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Version 1 ColdFire Debug (CF1_DEBUG)
Based on these features, BDM is useful for the following reasons:
22.4.1.1
Although certain BDM operations can occur in parallel with CPU operations, unrestricted BDM operation
requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of
priority. Recall that the default configuration of the Version 1 ColdFire core (CF1Core) defines the
occurrence of certain exception types to automatically generate a system reset. Some of these fault types
include illegal instructions, privilege errors, address errors, and bus error terminations, with the response
under control of the processor’s CPUCR[ARD, IRD] bits.
22-30
breakpoint trigger
HALT instruction
Fault-on-fault
Halt Source
•
•
•
•
Hardware
In-circuit emulation is not needed, so physical and electrical characteristics of the system are not
affected.
BDM is always available for debugging the system and provides a communication link for
upgrading firmware in existing systems.
Provides high-speed memory downloading, especially useful for flash programming
Provides absolute control of the processor, and thus the system. This feature allows quick hardware
debugging with the same tool set used for firmware development.
CPU Halt
Halt Timing
Immediate
Immediate
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Pending
Refers to the occurrence of any fault while exception processing. For example, a bus error is
signaled during exception stack frame writes or while fetching the first instruction in the
exception service routine.
Halt is made pending in the processor. The processor samples for pending halt and interrupt
conditions once per instruction. When a pending condition is asserted, the processor halts
execution at the next sample point.
CPUCR[ARD] = 1 Immediately enters halt.
CPUCR[ARD] = 0 Reset event is initiated.
supervisor mode
BDM enabled,
BDM enabled,
BDM disabled
user mode
Table 22-23. CPU Halt Sources
CPUCR[IRD] = 0
CPUCR[IRD] = 1 An illegal instruction exception is generated.
Processor immediately halts execution at the next instruction sample
point. The processor can be restarted by a BDM GO command.
Execution continues at the instruction after HALT.
CPUCR[IRD] = 0
CPUCR[IRD] = 1
CSR[UHE] = 0
CSR[UHE] = 0
CSR[UHE] = 1
A reset is initiated since attempted execution of an
illegal instruction
A reset event is initiated, because a privileged
instruction was attempted in user mode.
A privilege violation exception is generated.
Processor immediately halts execution at the next
instruction sample point. The processor can be
restarted by a BDM GO command. Execution
continues at the instruction after HALT.
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