mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 184

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Analog-to-Digital Converter (S08ADC12V1)
digital value of the analog signal. The result of the conversion is transferred to ADCRH and ADCRL upon
completion of the conversion algorithm.
If the bus frequency is less than the f
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the f
sample is enabled (ADLSMP=1).
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
9-18
The maximum total conversion time for different conditions is summarized in
Single or first continuous 10-bit or 12-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 10-bit or 12-bit
Subsequent continuous 10-bit or 12-bit;
Subsequent continuous 10-bit or 12-bit;
ADCK
Single or first continuous 8-bit
Single or first continuous 8-bit
Single or first continuous 8-bit
Single or first continuous 8-bit
Subsequent continuous 8-bit;
Subsequent continuous 8-bit;
frequency, precise sample time for continuous conversions cannot be guaranteed when long
Conversion Type
f
f
The ADCK frequency must be between f
maximum to meet ADC specifications.
BUS
BUS
f
f
BUS
BUS
> f
> f
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
> f
> f
ADCK
ADCK
ADCK
ADCK
Conversion time =
Table 9-13. Total Conversion Time vs. Control Conditions
/11
/11
Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles
ADCK
23 ADCK Cyc
frequency, precise sample time for continuous conversions
8 MHz/1
ADICLK
0x, 10
0x, 10
0x, 10
0x, 10
11
11
11
11
xx
xx
xx
xx
NOTE
ADLSMP
ADCK
+
0
0
1
1
0
0
1
1
0
0
1
1
5 bus Cyc
minimum and f
8 MHz
23 ADCK cycles + 5 bus clock cycles
43 ADCK cycles + 5 bus clock cycles
20 ADCK cycles + 5 bus clock cycles
40 ADCK cycles + 5 bus clock cycles
5 μs + 20 ADCK + 5 bus clock cycles
5 μs + 23 ADCK + 5 bus clock cycles
5 μs + 40 ADCK + 5 bus clock cycles
5 μs + 43 ADCK + 5 bus clock cycles
Max Total Conversion Time
= 3.5 μs
17 ADCK cycles
20 ADCK cycles
37 ADCK cycles
40 ADCK cycles
ADCK
Table
Freescale Semiconductor
9-13.