pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 103

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

1. After receive initialization is detected all data are ignored until a starting sequence
2. The octet synchronous (end) flag of one frame can be part of the (start) flag of the next
3. Here the start sequence is detected non-octet synchronously within a frame.
4. After MFL + 1 data bytes the further data are ignored and are neither stored in the RB
5. Data are formatted according to §2.8 of CCITT Q.921.
6. If a receive descriptor is full (4
For INV = 1 (channel inversion) all bits of the data stream (including DATA, FLAG) are
interpreted inversely e.g. 16 ‘ones’, ‘zero’ is interpreted as starting sequence then.
For Intel interface the only difference is in the receive data sections. They would be
Figure 57
User’s Manual
(16 ‘zeros’, ‘one’) is detected.
frame.
Note, that the first 00
as ordinary data and is included in BNO.
Between DATA 2 and DATA 3 the start and end flag are identical (shared flags
supported).
Therefore the frame belonging to DATA 3 is supposed to have ended non-octet
synchronously (NOB set in the 3
nor reported to the shared memory.
receive descriptor (5
memory.
31
XX
of 1 Desc
00
st
01
9D
0
31
XX XX 00 D3
of 2 Desc
th
H
nd
descriptor) even if no further data are to be given to the shared
character of the end flag is stored in the receive data section
0
th
rd
descriptor).
descriptor) the MUNICH32 branches to the next
31
AF
XX XX XX 03
of 3 Desc
3D
rd
103
00
01
0
31
56 9A FB 8F
of 4 Desc
th
Functional Description
0
31
XX
PEB 20320
of 6 Desc
00
th
5E
ITD05035
01.2000
BB
0