pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 47

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

PEB 20320
Functional Description
2.3
Basic Functional Principles
MUNICH32 is a Multichannel Network Interface Controller for HDLC, offering a variety
of additional features like subchanneling, data channels comprising of one or more
time slots, DMI 0, 1, 2 transparent or V.110/X.30 transmission and programmable rate
adaption. MUNICH32 performs formatting and deformatting operations in any network
configuration, where it implements, together with a microprocessor and a shared
memory, the bit oriented part (flag, bit stuffing, CRC check) of the layer 2 (data link
protocol level) functions of the OSI reference model.
The block diagram is shown in Figure 3. MUNICH32 is designed to handle up to 32 data
channels of a 1.536/1.544 Mbit/s T1/DS1 24-channel, 2.048-Mbit/s CEPT 32-channel or
a 4.096-Mbit/s 32-channel PCM highway. The device provides transmission for all bit
rates from 8 Kbit/s up to 2.048 Mbit/s of packed data in HDLC format or of data in a
transparent format supporting the DMI mode (0, 1, 2) or V.110/X.30 mode. Tristating of
the transmission line as well as switching a channelwise or complete loop are also
possible. An on-chip 64-channel DMA generator controls the exchange of data and
channel control information between the MUNICH32 and the external memory.
The MUNICH32 processes receive and transmit data independently for each time slot
and transmission direction respectively (blocks TF = Transmit Formatter, RD = Receive
Deformatter). The frame counters are reset by the rising edges of the RSP or TSP line.
The processing units TF and RD work with a multiplex management, i.e. there exists only
one protocol handler, which is used by all channels in a time sharing manner (see
Figure 24 and Figure 25). The actual configuration, e.g. transmission mode, channel
assignment, fill/mask code or state of the protocol handlers is retrieved from the
Configuration and State RAM (CSR) at the beginning of the time slot and reloaded to the
CSR at the end. The control unit (CD) controls the access to the CSR and allows writing
of reconfiguration information only if the continuous transfer of the configuration
information between the CSR and the formatters (TF and RD) will not be disturbed. In
receive direction, 32 unpacked data bits are first accumulated and then stored into an
on-chip receive buffer (RB) for transfer to the shared memory. As soon as the RB
receives 32 bits for a channel it requests access to the parallel microprocessor bus. The
on-chip transmit buffer (TB) is always kept full of data ready for transmission. The TB will
request more data when 32 bits become available in the ITBS. These buffers allows a
flexible access to the shared memory in order to prevent data underflow (Tx) and data
overflow (Rc).
The transmit buffer (TB) has a size of 64 long words (= 256 bytes). In this buffer, data of
8 PCM frames can be stored for each data channel. In this case, there are max. 1 ms
between access to the shared memory and data supply to the Transmit Formatter. In
order to meet these requirements a variable and programmable part of the buffer (ITBS)
must be allocated to each data channel (see Figure 26).
User’s Manual
47
01.2000