pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 42

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
Figure 20
Bus Management for Intel Bus Mode
Note 1: Bus Cycle means, that the MUNICH32 under consideration starts a read or
Note 2: In the Bus Management example it is assumed that the MUNICH32 under
Note 3: A typical configuration example for a system with several bus masters is given
HOLD (extern)
HOLD (intern)
HLDAO
write access at most 4 clock periods after HLDA is asserted after its HOLD. The
MUNICH32 terminates the cycle typically two clock periods after the last
bus cycle.
consideration has a higher priority than the other bus master. HOLD (internal) is
therefore the internal request generated by the MUNICH32, HOLD (external)
the signal on the external HOLD line, being the OR combination of the HOLD
signal generated by the MUNICH32 and the other bus master(s).
in Figure 4 and Figure 5.
SCLK
HLDA
Tristate
Tristate
gets the Bus
MUNICH32
Bus Cycle
Max. 4 Clock Periods
42
Tristate
Another Bus Master
gets the Bus
Functional Description
Tristate
requests
No Bus
PEB 20320
ITD03503
01.2000