pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 151

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

– receive off
– receive abort
User’s Manual
to ‘1’) followed by a branching to the new descriptor (FRDA) defined in the channel
specification of the CCS.
For HDLC, TMB, TMR the rest of a frame which was only partially transferred before
suspension of the receive descriptor is aborted, the new descriptor is related to the
next frame. An interrupt with FI, ERR is issued. For V.110/X.30 and TMA data bits
might get lost. An interrupt with ERR is issued.
RI = 0, RO = 1, RA = 0 (clears a previous receive abort condition, sets off condition,
affects only the serial interface)
This channel command sets the receiver into the receive off condition. The receive
channel is disabled completely at the serial interface, i.e. the receive deformatter RD
is reset and the receive buffer RB is not accessed for this channel. A currently
processed frame (HDLC, TMB, TMR mode) is not properly finished with any status
information. The data stored in the RB at that time is still transferred to the shared
memory.
After the receive off condition is cleared by another channel command:
• in HDLC, TMB, TMR (V.110/X.30, TMA) mode the device waits for a new frame (10-
RI = 0, RO = 1, RA = 1 (clears a previous receive off condition, sets a receive abort
condition, affects only the serial interface)
This receive channel command sets the receiver into the receive abort condition. In
this condition it receives (instead of the normally received bits)
irrespective of the INV bit.
• For HDLC: a currently processed frame is aborted after
octet frame, nothing) to begin and then starts filling RB again. If the receive off
command lead to an improper finishing of a frame (data, data), the new frame (data,
data) is concatenated with the finished one. To avoid this problem there are two
suggestions:
a) issue a receive abort channel command and wait for 32 (240, 8) bits for this
b) wait in the receive off condition until the RB is emptied for this channel (i.e. for at
This leads to
channel, leading to a RA set in the status of the frame and an interrupt with set FI
and ERR bits only or to an interrupt with set SF, FI and ERR bits. If the receiver was
logical ‘1’ bits for HDLC
logical ‘0’ bits for V.110/X.30, TMB, TMR
logical ‘0’ bits for unmasked bits in TMA mode
logical ‘1’ bits for masked bits in TMA mode
channel to be processed before issuing the receive off command.
most 8 PCM frames if the MUNICH32 has sufficient access to the shared
memory) and leave the receive off condition by a receive initialization command.
The receive off channel command is ignored in case of any kind of loop.
151
Detailed Register Description
7 received bits for this
PEB 20320
01.2000