pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 141

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

4.2.3
The next table shows the bit assignments for the interrupt information long word.
When an interrupt occurs MUNICH32 sets the INT bit and writes the interrupt information
and the channel number into the interrupt circular buffer. At the same time it generates
an interrupt pulse. The classes of error (for example host initiated interrupt or CRC error)
of a channel in one direction are treated independently of each other. If several interrupt
events coincide they will be indicated to the host with one shared interrupt.
Bit assignment for interrupt queue
There are 3 classes of bits in the interrupt:
1. Bits present in each interrupt:
User’s Manual
ARACK ARF HI
INT
31
15
INT:
VN(3:1): these bits are ‘000’ for version 1.1
INT
31
15
30
14
0
Interrupt Information
30
14
0
this bit is always set to ‘1’
29
13
VN3 VN2 VN1 FRC E7
29
13
Interrupt Information
28
12
28
12
FI
27
11
IFC
‘001’ for version 2.1
‘010’ for version 2.2
‘100’ for version 3.2
‘110’ for version 3.4
27
11
26
10
SF ERR FO
26
10
25
9
Interrupt Information
25
24
9
8
141
E6 E5 E4 E3 E2 E1 SB SA
24 23 22 21 20 19 18 17 16
23
8
7
7
0
22
6
6
0
Channel Number/Direction
Detailed Register Description
21
5
RT
5
20
4
4
Channel Number
19
3
3
18
2
PEB 20320
2
17
1
1
01.2000
16
0
X
0