pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 19

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

Pin Definitions and Functions (cont’d)
Pin No.
P-MQFP-160-1
40
44
45
46
61
User’s Manual
Symbol
INT/INT
RCLK
RSP
RDATA
SCLK
Output (O)
Input (I)
O
I
I
I
I
19
Function
Interrupt Request
An interrupt is given when a transmission/
reception error is detected, frames are
received or transmitted, or a host initiated
action is performed. The interrupt pulse
signal interacts with a write cycle to the
shared memory. The data written into the
interrupt queue contains the interrupt
specification.
The interrupt is active high for Intel bus
mode and active low for Motorola bus
mode.
Receive Clock
This clock provides the data clock for RDA
T1/DS1 24-channel
CEPT 32-channel
Receive Synchronization Pulse
This signal provides the reference for the
receive PCM frame synchronization. It
marks the first bit in the PCM frame.
Receive Data
Serial data is received at this PCM input
port. The MUNICH32 supports the T1/
DS1 24-channel PCM format, the CEPT
32-channel PCM format as well as a 32-
channel PCM format with 4.096-Mbit/s bit
rate.
System Clock
PCM highway system clock highway
frequency
32-channel
4.096 MHz
24-channel
24-channel
24-channel
32-channel
16.384 MHz 2.048 or
12.288 MHz 1.536 MHz
12.352 MHz 1.544 MHz
1.544 MHz
1.536 MHz
2.048 MHz
4.096 MHz
Introduction
PEB 20320
01.2000