pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 162

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
4.3
FE:
V.110
FE HOLD HI
31
15
30
Transmit Descriptor
14
0
Frame End; this bit is valid in all modes.
It indicates that after sending the data in the transmit data section
– the device generates an interrupt with FI bit set for HDLC, TMB, TMR, TMA
– the device then sends
13 12
29
0
28
0
ERR bit set for V.110/X.30
• (FNUM + 1)
• 7E, (FNUM – 1)
• 7E
• (FNUM + 1)
• 000
• (FNUM + 1)
• (FNUM +1)
• three frames with synchronization errors for V.110/X.30
before starting with the data of the next transmit descriptor. If the
data of the next transmit descriptor are not available in time (e.g.
because the descriptor has FE and HOLD set) the device sends
the interframe time-fill indefinitely.
CSM
27
11
H
Next Transmit Descriptor Pointer
Next Transmit Descriptor Pointer
26
10
Transmit Data Pointer
Transmit Data Pointer
25
FF
9
7E
00
TFLAG
H
H
H
24
FF
8
162
H
, 7E for HDLC, IFTF = 1, FNUM
23
7
for HDLC, IFTF = 0
for HDLC, IFTF = 1, FNUM = 0
for TMB, TMR (FNUM
for TMR, FNUM = 0
for TMA, FA = 1
for TMA, FA = 0
NO
22
6
FNUM
Detailed Register Description
21
5
20
4
19
3
18
2
PEB 20320
1)
17
1
1
01.2000
16
0