pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 188
pef20320
Manufacturer Part Number
pef20320
Description
Multichannel Network Interface Controller For Hdlc With 32 Channels
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEF20320.pdf
(252 pages)
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PEB 20320
Application Notes
The LAN controller’s (i82596) bus timing also needs to be adapted. The address lines
A1, AO, Size 0 and Size 1 need to be generated, because the LAN controller performs
8 bit and 16 bit cycles as well as 32 bit cycles. There are also some non standard bus
signals for the LAN controller, that have to be generated. Furthermore the System Clock
and the Bus Clock have to be synchronized. All necessary glue logic for the
LAN controller is realized in four devices Gal 16V8.
5.2.3
Software
The software is based on a message oriented device driver system. The device driver
modules and application modules have a structure that allows to access them via
defined entry points.
Module Entry Points
Two Entry points offer access to the DDMs. Messages can be sent to the DDM via the
Message Entry Point. A hardware interrupt causes the program to branch to the Interrupt
Entry Point. The APM also offers access via a Message Entry Point, but since the APM
does not control any hardware, there does not exist any Interrupt Entry Point.
Device Driver System
Message
Message
Device Driver Module
Application Module
Interrupt
Hardware
ITS08289
Figure 91
Module Entry Points
User’s Manual
188
01.2000
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