pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 132

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
Transmit Descriptor
FNUM = 00
TMB.
The E-, S-, X-bits are all set to zero internally by the reset. The receiver is set into the
ITF/IDLE state for all channels, i.e. it assumes that on the line there are ‘1’s as interframe
time-fill for HDLC.
3.2
After reset MUNICH32 remains in the initial state until the microprocessor generates an
action request. In the action specification the initialization sequence is defined. The
sequence can be split up into individual procedures of each channel or in one single
procedure to initialize all channels at the same time. For all procedures the time slot
assignment and the selected channel specifications are loaded into the CSR-RAM. To
prevent malfunction the initialization of the link lists and the allocation of the buffer size
to the channels has to be specified before the transmission can be started. The interrupt
queue must be established as well. MUNICH32 assumes that time slot 0 starts on the
receive and transmit lines. They can be resynchronized by 2 rising edges of TSP and
RSP respectively. The first rising edge of TSP/RSP should not take place within the first
1000 SCLK clock cycles after deassertion of the reset pin.
Before this resynchronization the host should neither remove RO = 1, TO = 1 nor set
LOOP or LOOPI to ‘1’ for any logical channel. During this time any incoming data is
ignored, the transmit data line tristated.
For each action service the device first reads the control start address in the control and
configuration section which is located under a fixed address determined by the input
signals (CI(4:0)).
The values of CI(4:0) can be changed during operation. The values are used after the
next falling edge of AR.
CI4
CI3
CI2
CI1
CI0
for example CI(4:0)
ADDRESS
Initialization Procedure
H
, i.e. shared flags in HDLC, only eight zero bits between sent frames for
is the polarity of A31 … A22
is the polarity of A21 … A16
is the polarity of A15 … A4
is the polarity of A3
is the polarity of A2
A0, A1 = 0
=
=
10101
1111.1111.1100.0000.1111.1111.1111.0100
132
Operational Description
PEB 20320
01.2000