pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 33

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

Figure 12
T1/DS1 Mode PCM Frame Timing 1.544 MHz
Note 1: A
Note 2: The fill/mask bit for the F-bit is not defined. TDATA is tristate for the F-bit, and
Note 3: TSP and RSP must have one single rising and falling edge during a
User’s Manual
FILL/MASK
FILL/MASK
SLOT 23
SLOT 23
RDATA
TDATA
RCLK
TCLK
RSP
TSP
TMB, TMR, V.110/X.30) or received as ‘1’-bit (TMA; one overwrite).
the F-bit is ignored in the receive direction.
125 s PCM frame.
6
6
F
DATA
7
7
0
box in a bit of the RDATA line means that this bit is ignored (HDLC,
1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
PCM - Frame
T1/DS1 - Mode Transmit Frame Timing
T1/DS1 - Mode Receive Frame Timing
F
F
SLOT 0
DATA DATA
0
0
1
1
2
2
DATA
SLOT 0
SLOT 0
3
3
SLOT 1
4
4
33
DATA DATA
5
5
125 µs
6
6
7
7
Fill/Mask : Slot 0
Fill/Mask : Slot 0
1 0 0 1 1 0 0 0
1 1 0 1 0 1 1 0
Functional Description
SLOT 1
SLOT 1
SLOT 23
PEB 20320
ITD03496
01.2000