pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 171

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

NI
ILN
IL
I
IF
I, IF, IL, ILN
Note: For HDLC, TMB, TMR the status word is only valid if the FE bit is set.
The meaning of the individual status bits is as follows:
SF = 1
LOSS = 1
CRCO = 1
NOB = 1
LFD = 1
RA = 1
ROF = 1
Note: If ROF without FO interrupt is generated for a channel
User’s Manual
• for HDLC, TMB, TMR only the last part of one frame has been lost.
• For V.110/X.30 only data but no status information (change E-, S-, X-bits, Loss)
has been lost.
means the bit may be ‘1’ or ‘0’ but does not cause an interrupt with
set ERR bit.
means that it may be ‘1’ or ‘0’ but should not be evaluated if LFD or NOB
is also ‘1’.
means that it may be ‘1’ or ‘0’ but should not be evaluated if LFD = 1.
means that it may ‘1’ or ‘0’.
means that it may be ‘1’ only after a fast receive abort channel command
or detection of a HOLD bit in the current receive descriptor.
lead to an interrupt with ERR bit set.
(HDLC mode with CS = 0 only):
The device has received a frame with
i.e. BNO was 1 or 2.
Three contiguous frames with errors in the synchronization pattern were
detected.
A frame with a CRC error was detected CRCO = 0 means the frame had
no CRC error.
A frame whose bit content was not divisible by 8 was detected.
NOB = 0 means that the frame content was divisible by 8.
Long frame detected. If this bit is set a frame whose bit content
was > MFL was detected and aborted. The reception will be continued as
soon as a flag is recognized.
Receive Abort; this bit indicates that
for HDLC: the frame was ended by an abort flag (7F
abort command or a fast receive channel command or by a HOLD bit in
the current receive descriptor.
for V.110/X.30, TMB, TMR, TMA that the frame or data were aborted by
a fast receive abort channel command or a HOLD bit set in the current
receive descriptor.
An overflow of the internal buffer RB has occurred and lead to a
loss of data.
32 bit between start flag and end flag or end abort flag for CRC16
48 bit between start flag and end flag or end abort flag for CRC32
171
Detailed Register Description
H
) or by a receive
PEB 20320
01.2000