pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 9

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

• Processor Interface
User’s Manual
– V.110/X.30 Protocol
– Transparent Mode A
– Transparent Mode B
– Transparent Mode R
– Protocol Independent
– ON-CHIP 64-channel DMA controller with buffer chaining capability.
– Compatible with Motorola 68020 processor family and
– 32 bit data bus and 32 bit address bus (4 Gbyte RAM addressable, Motorola and
– Intel parity mode with data byte parity (4 parity bits)
– Interrupt-circular buffer with variable size
– Maskable interrupts for each channel
–
– Automatic synchronization in receive direction, automatic generation of
– E / S / X bits freely programmable in transmit direction, van be changed
– Generation/detection of loss of synchronism
– Bit framing with network data rates from 600 bit/s up to 38.4 Kbit/s
– Slot synchronous transparent transmission/reception without frame structure
– Bit-overwrite with fill/mask bits
– Flag generation, flag stuffing, flag extraction, flag generation
– Transparent transmission/reception in frames delimited by 00
– Shared opening and closing flag
– Flag stuffing, flag detection, flag generation in the abort case
– Error detection (non octet frame content, short frame, long frame)
– Transparent transmission/reception with GSM 08.60 frame structure
– Automatic 0000
– Support of 40, 39
– Error detection (non octet frame content, short frame, long frame)
– Channel inversion (data, flags, IDLE code)
– Format conventions as in CCITT Q.921 § 2.8
– Data over- and underflow detected
Intel 32-bit processor (80386).
Intel non-parity) or 28 bit address bus (256 Mbyte RAM addressable, Intel parity)
– Parity check for read accesses
– Parity generation for write accesses
P interface buffer of depth 16 long words for adaptive bus occupation
the synchronization pattern in transmit direction
during transmission; changes monitored and reported in receive direction
in the abort case with programmable flag
H
1
flag generation/detection
/
2
, 40
1
/
2
octet frames
9
H
flags
Introduction
PEB 20320
01.2000