pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 39

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

2.2.1
The Intel mode has two submodes – parity mode (even parity) and non parity mode – to
be chosen by strapping PM to ‘1’ or ‘0’ respectively.
In Intel mode the lower (higher) ordered byte of a long word (D31 … D0) is assigned to
the lower (higher) ordered physical address.
The read or write bus cycle is controlled by the signals W/R, ADS and READY as shown
in Figure 18, Figure 19. Each bus cycle consists of two bus states (S1, S2). During state
S1 the address signals and bus cycle definition signals are driven valid. Simultaneously,
the address status ADS is asserted to indicate their availability. The bus cycles are
terminated by asserting READY. READY is ignored on the first bus state S1 and
sampled at the end of the following state S2. If READY is not asserted in S2 then wait
cycles SW are inserted until a bus cycle end is detected. During a read cycle the
MUNICH32 floats its data signals to allow external memory to drive the data bus.
The input data and parity bits DP3–0 (if parity mode is selected) is latched when READY
is asserted. During a write cycle MUNICH32 drives the data signals and parity bits DP3–
0 (if parity mode is selected) beginning in the second clock period of S1 until the first
clock period following the cycle acknowledgment READY. If a bus cycle error indicated
by BERR has occurred, the MUNICH32 terminates the bus cycle. In case of a read cycle
in the control and configuration section an action request fail interrupt is generated and
the action is suspended. In case of a read cycle in the transmit data section the
corresponding frame is aborted and a FO interrupt is generated. In all other cases of read
or write cycles terminated with an error condition no actions are performed.
A 4-bit data byte parity bus DP3–0 is used in Intel mode if parity mode is selected by
strapping PM to ‘1’. During a read access DP3–0 is supposed to contain the parity of
D(31:24), D(23:16), D(15:8) and D(7:0) respectively. A low active output PCHK indicates
whether the parity was correct (PCHK = 1) or wrong (PCHK = 0) in the clock cycle after
the data/parity is latched. PCHK stays low 1 or 2 clock cycles. No further action is taken
as consequence to a parity fail.
As the memory access is performed by using one common system bus, bus
management is done with the signals HOLD, HLDA and HLDAO as shown in Figure 20.
The wired or HOLD line is driven high whenever one of the MUNICH32s has to perform
a bus transfer. The activated HOLD ACKNOWLEDGE indicates that the bus control will
be released. If the specific device has activated the HOLD itself, it will start the memory
access. Otherwise it will pass the signal to the next cascaded device. Several memory
accesses may be required if the MUNICH32 has not been granted access recently.
In this
each device will generate four memory cycles, giving a total of 16 cycles per
HOLD/HLDA/HLDAO tenure. In order to prevent blocking in the case of continuous
request by one device, the MUNICH32 does not generate another HOLD REQUEST
before the HOLD ACKNOWLEDGE has been deactivated.
User’s Manual
Intel Mode
example
of
four
MUNICH32
39
devices
sharing
Functional Description
the
PEB 20320
same
01.2000
bus,