pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 241

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

The trailing edge of the reset starts the last part of the internal reset sequence and takes
about 12 SCLK cycles. It is not allowed to give an action request (AR) during these first
12 SCLK cycles after the trailing edge of signal RESET.
JTAG-Boundary Scan Timing
Figure 126
JTAG-Boundary Scan Timing
Table 20
Intel Bus Timing
No. Parameter
58
59
60
61
62
63
64
65
User’s Manual
JTEST0 (TCK) period
JTEST0 (TCK) high time
JTEST0 (TCK) low time
JTEST1 (TMS) setup time
JTEST1 (TMS) hold time
JTEST2 (TDI) setup time
JTEST2 (TDI) hold time
JTEST3 (TDO) valid delay
JTEST0 (TCK)
JTEST1 (TMS)
JTEST2 (TDI)
JTEST3 (TDO)
59
241
58
65
60
63
61
min.
166
80
80
15
10
15
15
30
62
64
Electrical Characteristics
Limit Values
max.
inf
–
–
–
–
–
–
–
ITD03512
PEB 20320
01.2000
Unit
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–
–
–
–
–
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