pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 131

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

3
3.1
Upon reset MUNICH32 is set to its initial state. The active high system reset clears the
internal logic and causes MUNICH32 to tristate all output lines. Channel processing is
deactivated. After reset all buffers are empty and no buffer size of TB is allocated to the
channels. The DMA controller state is set to the hold condition for all link lists. The
descriptor and data pointers remain at a random value.
The bits RO and TO are set to ‘1’ and RA and TA are set to ‘0’ for all logical channels by
reset. All time slots are connected to the logical channel 0 and the following configuration
is set:
Action Specification
LOC = LOOP = LOOPI = 0
PCM = T1/DS1
MFL = 0
Time Slot Assignment
fill/mask = 00
RTI, TTI = 0
channel number = 00
Channel Specification
MODE = 00, i.e. TMA
FA = 0
IFTF = 0
CRC = 0
INV = 0
TRV = 00,
RA = 0
TA = 0
TH = 0
User’s Manual
RO = 1
TO = 1
Operational Description
Reset State
H
, i.e. all bits masked/set to ‘1’
24-channel 1.536 Mbit/s (000)
H
131
Operational Description
PEB 20320
01.2000