pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 163

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

HOLD:
HI:
NO:
V.110:
User’s Manual
If the MUNICH32 detects a hold bit it
– generates an interrupt with ERR bit set if FE = 0 or V.110/X.30 mode
– sends the data in the current transmit data section
– generates the FCS bits for HDLC and CS = 0 and CSM = 0
– the device then sends at least
– It polls the HOLD bit and the next transmit descriptor address, but does no
– The device sends interframe time-fill until HOLD = 0 is polled.
The HOLD condition is also discarded if a transmit jump, fast transmit abort
or transmit initialization command is detected during the polling. The
MUNICH32 then branches to the transmit descriptor determined by FTDA
even though the HOLD bit of the current transmit descriptor may still be ‘1’.
Host initiated Interrupt; if the HI bit is set, MUNICH32 generates an interrupt
with set HI bit after transferring all data bytes.
This byte number defines the number of bytes stored in the data section to be
transmitted. A transmit descriptor and the corresponding data section must
contain at least either one data byte or a frame end indication.
Otherwise an interrupt with set ERR bit is generated.
This bit indicates that in the corresponding data section the E-, S- and X-bits
of the following V.110/X.30 frame are stored. MUNICH32 reads these bits and
inserts them into the next possible V.110/X.30 frame. The data section may
contain only two bytes specified in the next figure.
The first transmit descriptor after a transmit initialization channel command
must have this bit set if it revives the channel from a transmit off condition or
after a pulse at the reset pin.
branch to a new descriptor until the HOLD bit is reset. The next transmit
descriptor address is read but not interpreted as long as HOLD = 1.
Therefore it can be changed together with setting HOLD = 0.
The polling occurs at most every 8 valid clock cycles of the channel and
corresponds with internal requests from TF to TB.
• (FNUM + 1)
• 7E, FNUM
• (FNUM + 1)
• 0000
• (FNUM + 1)
• (FNUM + 1)
• three frames with synchronization errors for V.110/X.30.
H
FF
7E
00
TFLAG
FF
H
H
H
H
163
for HDLC, IFTF = 0
for HDLC, IFTF = 1
for TMB, TMR (FNUM
for TMR, FNUM = 0
for TMA, FA = 1
for TMA, FA = 0
Detailed Register Description
PEB 20320
1)
01.2000