pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 15

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

Pin Definitions and Functions (cont’d)
Pin No.
P-MQFP-160-1
90
75
User’s Manual
Symbol
W/R
R/W
READY
DSACK
Output (O)
Input (I)
O
O
I
I
15
Function
Write/Read (Intel bus mode)
This signal distinguishes write from read
operations.
Read/Write (Motorola bus mode)
This signal distinguishes between read
and write operations.
In both cases this signal is tristate when
unused.
Ready (Intel bus mode)
This signal indicates that the current bus
cycle is complete. When READY is
asserted during a read cycle the
MUNICH32 latches the input data and
terminates the cycle. When READY is
asserted during a write cycle the
MUNICH32 terminates the cycle.
Data Transfer Acknowledge (Motorola
bus mode)
This active low input indicates that a data
transfer may be performed. During a read
cycle data becomes valid at the falling
edge of DSACK. The data is latched
internally and the bus cycle is terminated.
During a write cycle the falling edge of
DSACK marks the latching of data and the
bus cycle is terminated.
Introduction
PEB 20320
01.2000