pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 17

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

Pin Definitions and Functions (cont’d)
Pin No.
P-MQFP-160-1
82
79
81
User’s Manual
Symbol
HOLD
BR
HLDA
BG
BGACK
PM
Output (O)
Input (I)
I/O
I/O
O
I
I
I
17
Function
Bus Hold Request (Intel bus mode)
This signal is driven high when the
MUNICH32 requests the control of the
bus.
Bus Request (Motorola bus mode)
This signal is driven low when the
MUNICH32 requests the control of the bus
and is interpreted when another
MUNICH32 wants to be the bus master.
Bus Hold Acknowledge (Intel bus mode)
This active high signal indicates that the
processor has released the control of the
bus. The MUNICH32 starts the bus cycles.
Bus Grant (Motorola bus mode)
This active low signal indicates that the
MUNICH32 may assume the bus
mastership.
Bus Grant Acknowledge (Motorola bus
mode)
This signal is driven low by the device,
when it has become the bus master. It also
informs the MUNICH32 whether another
device is bus master.
Parity Mode (Intel bus mode)
This signal has to be strapped to
before reset to enable the Intel parity
mode or to
Intel non-parity mode. It has to be left
strapped during reset and operation.
V
SS
before reset to enable the
Introduction
PEB 20320
V
DD
01.2000