pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 179

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

Generate AR Pulse and wait for INT signal (set up TS0 and CH0).
Read interrupt queue:
ICQ:
Set ASP for Internal Channelwise Loop test
ASP:
Generate AR Pulse and wait for INT signal.
Read interrupt queue:
ICQ:
Clear HOLD bit in FTDA (allow frame to Tx over Internal Chnl. Loop).
Read interrupt queue:
ICQ:
Read receive descriptors:
FRDA:
User’s Manual
9000-8000
9000-1000
A104-0028
9000-8000
9000-1000
9000-082020
9000-1000
9000-1020
0020-0000
4020-0000
RcvDtaPtr
NxtRDPtr
0020-0000
4020-0000
RcvDtaPtr
NxtRDPtr
0020-0000
C000-0000
RcvDtaPtr
NxtRDPtr
4020-0000
0000-0000
RcvDtaPtr
0000-0000
179
;Action Request Acknowledge
;V2.2 (V2.1 = 8800-8000)
;Polls HOLD bit of 1st Tx Desc.
;CEPT, MFL=260, Int. Chnl loop
;Action Request Acknowledge
;Polls HOLD bit of 1st Tx Desc.
;Rc ITF state change
;End of Tx frame, polling HOLD
;Rc frame complete
;C = 1, NO = BNO
abcdefghijklmnop
qrstuvwxyz012345
;C = 1, NO=BNO
ABCDEFGHIJKLMNOP
QRSTUVWXYZ987654
;FE, C = 1, BNO = 0
;empty! (p. 139 User’s Manual -
32 byte
data block
bit of Tx desc.
FE description)
Application Notes
PEB 20320
01.2000