pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 187

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

Bus Timing Adaptation
The bus controller manages memory accesses of all bus masters (CPU, MUNICH32 or
LAN controller). The bus controller timing is Motorola 68040 specific. The MUNICH32
bus interface is either Intel specific or Motorola 68020/030 specific. Therefore the
MUNICH32 bus timing needs to be adapted by using simple glue logic. One Gate Array
Logic (Gal16V8, 15 ns) contains all necessary logic.
The MUNICH32 Address Strobe (AS) signal determines valid addresses on the bus. The
equivalent Motorola 68040 control signal is the Transfer Start (TS). During MUNICH32
write cycles valid data on the bus is indicated with the Data Strobe (DS) signal.
MUNICH32 write and read bus cycles are terminated with the Data Transfer
Acknowledge (DSACK) signal. For the Motorola 68040 the end of a bus cycle is
indicated by the Transfer Acknowledge (TA) signal.
During MUNICH32 bus cycles the MUNICH32 output signal AS is used to generate the
bus controller input signal TS. The TS is deasserted with the MUNICH32 input DSACK
rising edge. Since all bus cycles have the same length the DSACK signal is generated
two bus clock cycles after AS is detected low. TS is tristated, if the MUNICH32 is not
busmaster. This signal is driven by another bus master during that time.
Figure 90
MUNICH32 Timing Adaption
1)
User’s Manual
See also Chapter 5.2.6.
BCLK
SCLK
TS
TA
Addr
Data
AS
DSACK
1)
187
Application Notes
ITD08288
PEB 20320
01.2000