pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 146

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
The following table shows which interrupt bits are masked by which bits in the channel
specification.
Receive
Transmit
Receive
Transmit
ARACK ARF HI
INT
31
15
30
14
1.2 HDLC, TMB, TMR
2.1 V.110/X.30
2.2 V.110/X.30
3.1 TMA
3.2 see Chapter 1.2
VN3 VN2 VN1 FRC
29
frames or change of interframe time-fill informations due to inaccessibility
of the internal buffer RB.
The MUNICH32 is unable to access the shared memory in time or has
detected a bus cycle error (BERR = 0) during a read access on the
transmit data section. The current erroneous frame is aborted with a ‘0’
and 14 ‘1’ for HDLC, with 00 for TMB and 0000 for TMR; afterwards
interframe time fill is sent until the MUNICH32 can access again the
shared memory. The MUNICH32 will read the transmit data from the
location which should be accessed before the Tx-FO or BERR happened
and transmit the rest of the erroneous frame.
The MUNICH32 has discarded a loss of synchronism information or a
change of a E-, S-, X-bits information due to inaccessibility of the internal
buffer RB.
The MUNICH32 is unable to access the shared memory in time or has
detected a bus cycle error (BERR = 0) during a read access on the
transmit data section. It generates 3 10-octet frames with framing errors
and restarts with the next error-free transmit data.
The MUNICH32 has discarded data due to inaccessibility of the internal
buffer RB.
13
28
FIR IFC SFE RE
FIT
12
FI IFC SF ERR FO
27
11
–
10
26
–
TE
E7 E6 E5 E4 E3 E2 E1 SB SA
25
9
Transmit Direction
Receive Direction
Transmit Direction
Receive Direction
146
24
RE
TE
8
23
0
7
22
6
0
Detailed Register Description
CH
21
–
RT
5
20
4
Channel Number
19
3
18
PEB 20320
2
17
1
01.2000
16
X
0