pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 240

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
Table 18
No.
51
52
53
Note: If
System Interface Timing
Figure 125
Table 19
No.
55
56
57
After power up a logical ‘1’ at the reset pin of the MUNICH V3.4 sets the device into a
reset state where the complete microprocessor bus interface is tristated and the internal
reset sequence is started.
the frequency of the clock SCLK the equations
and
describe the allowed range of frequencies for
Parameter
Reset to first action request delay 12 SCLK cycles
AR# pulse width
Reset pulse width
Parameter
Cycle period
Clock low time
Clock high time
f
AR
RESET
T
7.996
3.998
is the frequency of the clock TCLK,
max (
max (
f
f
T
T
,
,
f
f
R
R
)
)
f
f
S
S
57
16.667 MHZ for CEPT, T1, E1 PCM mode
16.667 MHZ for 4.096 MHz PCM mode
56
min.
50
25
25
240
min.
2 SCLK cycles
2 SCLK cycles
f
R
Limit Values
the frequency of the clock RCLK and
f
55
S
max
–
–
–
.
Limit Values
Electrical Characteristics
max.
–
5 SCLK cycles
–
first action
request AR
after reset
Unit
ns
ns
ns
PEB 20320
ITT10668
01.2000
Unit
–
–
–
f
S