pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 214

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
5.3
The MUNICH32 may be used in different system architectures depending mainly on how
the data buffers are shared between the interacting bus masters. In the following the
memory bus occupancy is calculated for a system, where the MUNICH32 is directly
coupled with a 32-bit CPU (compatible to either Motorola 68020 or Intel 386) sharing one
common local CPU bus and translated via an appropriate system bus controller sharing
the system memory as well. This example system looks very similar to the one depicted
in the Figure 7 and Figure 9 of Chapter 1. In this case it is easier to estimate the
behavior of the complete system.
In addition to that, the following assumptions are made about the communication
parameters:
– HDLC operating mode
– the MUNICH is clocked with SCLK = 16 MHz
– the bus arbitration time is estimated to be about 4 extra clock cycles (SCLK) for every
– the data buffer size allocated in the data buffer pool is 32 bytes for transmit and
– a full duplex connection with up to 32
– the data size per HDLC frame is defined to be without the shared flag and the two CRC
– when the data size exceeds 32 bytes, more than one descriptor is needed for a single
– an interrupt information is generated for every descriptor.
The MUNICH32 needs the following 32-bit memory accesses (read or write):
10 MUNICH32 memory accesses (typical is 10 to 16)
receive descriptors
(shared flags)
bytes
frame
Receive:
Memory Bus Occupancy for a Single MUNICH32
read descriptor
write current descriptor address
write status
write interrupt
write data (size)
214
64 Kbit/s channels and heavy traffic load
3
1
1
1
accesses size
1
1
1
1
2
:
Application Notes
1
2
3
4
5
:
PEB 20320
01.2000