pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 143

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

Where ‘1’
The meaning of the interrupt bits depend on the mode. We therefore will discuss them
bit for bit and indicate the different meanings in the different modes.
FRC:
Ex, Sx, X:
HI:
FI:
User’s Manual
‘0’
‘F’
‘R’ means a bit that can only be set in the receive direction, i.e. may only
‘T’
‘TR’ means a bit that can occur in receive or transmit direction
‘G’ means a bit of an activation request interrupt which cannot be
‘X’
1.1 HDLC, TMB, TMR
1.2 HDLC, TMB, TMR, TMA Transmit Direction:
means that the bit is always ‘1’ for this mode
means that the bit is always ‘0’ for this mode
means the bit is fixed by the version number
be ‘1’ if RT is ‘1’
means a bit that can only occur in transmit direction, i.e. may only
be ‘1’ if RT is ‘0’
‘G’ in a channel specific interrupt
means a bit fixed by the channel and direction (receive, transmit)
of the event it belongs to.
(V.110/X.30 mode, receive direction only)
(all modes, all direction)
Change of the framing (E, S, X) bits of the V.110/X.30 frame detected.
This interrupt is generated whenever a change in the E-, S-, X-bits is
detected, but at most one time within one frame of 10 octets, even if there
is more than one change within the frame. After detecting a receive abort
channel command for one 10-octet frame FRC is also issued.
(V.110/X.30 mode, receive direction only, only in conjunction with FRC)
The value of the bits Ex, Sx, X in the received V.110/X.30 frame. If a
value changes, e.g. 2 times within the same frame only the final change
is reported.
If the change was caused by a receive abort channel command all bits
are 0.
Host initiated Interrupt; this bit is set when the MUNICH32 detects the
HI bit in the receive or transmit descriptor and branches to the next
descriptor, or starts polling the hold bit if set.
FI = 1 indicates, that a frame has been received completely or was
stopped by a receive abort channel command or fast receive abort or a
HOLD in a receive descriptor. It is set when the MUNICH32 branches
from the last descriptor belonging to the frame to the first descriptor of a
new frame. It is also set when the descriptor in which the frame finished
contained a hold bit, the interrupt is then issued when the MUNICH32
starts polling the hold bit.
issued if the FE bit is detected in the transmit descriptor. It is set when
the MUNICH32 branches to the next transmit descriptor, belonging to a
Receive Direction:
143
Detailed Register Description
PEB 20320
01.2000