pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 186

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
Bus Arbitration
Since three devices are using the bus it is necessary to implement a bus arbitration.
Each bus master requests bus mastership and awaits bus control given to it by the
arbiter. The bus arbitration protocol is also Motorola specific. The intel specific signals of
the LAN controller (i82596) are translated into Motorola specific signals. The bus
arbitration is realized in two devices GAL16V8 (15 ns), both containing a Finite State
Machine. Arbiter 1 gives bus mastership to the CPU whenever no other bus master
requests bus mastership. If either the MUNICH32 or the LAN controller requests bus
mastership the arbiter 2 gives a bus request to the arbiter 1. Arbiter 1 forces the CPU to
release the bus and gives bus mastership to arbiter 2. Arbiter 2 then responds to
MUNICH32 or LAN controller. In this solution the priority of the MUNICH32 is higher than
that of the LAN controller. Consequently if both alternate bus masters request bus
mastership at the same time, bus mastership will be given to the MUNICH32. The LAN
controller has to wait until MUNICH32 has finished his accesses and arbiter 1 returns the
bus to the CPU. It might happen, that some Ethernet frames get lost, because the
LAN controller can not get access to the bus in time, but the loss of incoming data from
the ISDN (where fees have to be paid) is minimized.
Figure 89
Bus Arbitration
MUNICH32
Arbiter 1
Arbiter 2
CPU
186
Application Notes
i82596
ITS08287
PEB 20320
01.2000