pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 96

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
Figure 53
Note: 1. After Receive Initialization is detected all data are ignored until the starting
2. Data are formatted according to §2.8 of CCITT Q.921.
3. The octet synchronous (end) flag of one frame can be part of the (start) flag of
4. Here the sequence 0000 0000 1 is detected non-octet synchronously.
5. After MFL + 1 data bytes the further data are ignored and are neither stored in
6. If a receive descriptor is full (4
sequence 0000 0000 1 is detected.
the next frame. Between DATA 1 and DATA 3 they are identical (shared flags
supported).
Therefore the frame belonging to DATA 3 is supposed to have ended non-octet
synchronously (NOB set in the 3
the RB nor reported to the shared memory. The receiver waits for the next
sequence 0000 0000 1 to come.
receive descriptor (5
shared memory.
31
20080000
40080000
4 Desc
th
DATA 4
0
Last Access of a LFD Frame
should be Ignored
31
01
Generate HI-Int.
8800202A
7F
FE
th
DF
31
0
desc.) even if no further data are to be given to the
5
C0000C00
00040000
th
Desc
LFD,
NOB
0
6
th
rd
desc.) the MUNICH32 branches to the next
96
descriptor).
Generate FI,
8800122A
31
00FC0000
C0020000
6
th
ERR-Int.
Desc
DATA 5
0
Functional Description
31
B5 54 XX XX
Generate FI-Int.
8800102A
ITD04567
0
PEB 20320
01.2000