pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 152

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
Note 1: It is advisable to clear the receive abort condition via a receive off command for
– receive jump
– receive initialization
• For V.110/X.30: if the receiver was in the synchronized frame state it will go to the
• For TMB: a currently processed frame is aborted after
• For TMR: a currently processed frame is aborted after
• For TMA: the device receives the inverse of the fill/mask bits programmed for this
RI = 1, RO = 0, RA = 0 (clears a previous receive abort or receive off condition, affects
only the DMA interface)
During normal operation branching to a new descriptor (FRDA) is possible without
interrupting the current descriptor and aborting the received frame (HDLC, TMB,
TMR) or received data (V.110/X.30, TMA).
The DMA controller will proceed finishing the current receive descriptor as usual either
with a frame end condition or with the corresponding data buffer completely filled and
afterwards branch to the new descriptor specified by FRDA. Thus a received frame
may be splitted on ‘old’ and ‘new’ descriptors.
RI = 1, RO = 0, RA = 1 (clears a previous receive abort or receive off condition, affects
the DMA and serial interface)
Before the MUNICH32 has got a receive initialization command it will not receive
anything properly in a channel. This command should therefore be the first channel
command after a pulse at the reset pin for a channel to be used. FRDA is then the
address of the starting point of the receive descriptor chaining list.
If the command is issued during normal operation it only affects the DMA interface.
The current receive descriptor is suspended without writing the second long word with
the status, no interrupt is generated. For HDLC, TMB, TMR the rest of a frame which
was only partially transferred before the suspension of the receive descriptor is
in the flag interframe time-fill state it will lead to an interrupt with set IFC bit after
received bits.
unsynchronized state after
current receive descriptor. It will also issue an interrupt with set ERR bit and (unless
all E-, S-, X-bits were 0 previously) issue one or two interrupts with FRC set and
having all E-, S-, X-bits at 0 in the last one.
channel, leading to an interrupt with FI set but ERR on 0, the status of this frame is
always 00
channel, leading to an interrupt with FI set but ERR on 0, the status of this frame is
always 00
channels.
2. After issuing a receive abort channel command it is advisable to stay in this
V.110/X.30 mode, the TMB and the TMR mode.
condition during at least 16, 240, 16, 32, 8 bits of the channel for HDLC, V.110/
X.30, TMB, TMR, TMA respectively.
H
H
.
.
240 bits and issue a LOSS bit in the status of the
152
Detailed Register Description
15 received bits for this
31 received bits for this
PEB 20320
01.2000
15