pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 122

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
Options
The different options for this mode are the framing pattern as shown in Table 2 to
Table 5 is programmed by the bits TRV.
Interrupts
The possible interrupts for this mode are
FRC: issued if the receiver has detected a change of S-, X-, E-bits; the value of the bits
HI:
ERR: issued if one of the following receive errors has occurred:
FO: issued if due to inaccessibility of the internal buffer (RB) one or more changes of
Example
V.110/X.30 channel with
CS = 0
INV = 0
CRC = 0
TRV = 00
FA = 0
MODE = 10
Motorola interface
Channel No. D
E7, …, E1, S8 for SA and S9 for SB and the second occurrence of X within the 10-
octet frame is reported within the same interrupt.
(maskable by CH in the channel specification
issued if the HI bit is detected in the transmit descriptor (not maskable).
– a fast receive abort channel command was issued (this leads to a setting of the
– data could only partly be stored due to internal buffer overflow of RB
– 3 consecutive frames had an error in the synchronization
– the HOLD bit in the receive descriptor was detected (this leads to a setting of the
E-, S-, X-bits and/or loss of synchronism information have been lost.
(maskable by RE in the channel specification)
(maskable by RE in the channel specification)
RA bit in the status byte)
pattern (loss of synchronism)
RA bit in status in the receive descriptor).
(V.110/X.30)
(required)
(600 bit/s)
122
Functional Description
PEB 20320
01.2000