pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 220

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
6
6.1
If you use the i386 as host processor with the MUNICH32 in a common bus system you
have to adapt the different frequencies of the devices. The MUNICH32 works e.g. with
a fixed frequency of 16.384 MHz in CEPT 32 channel PCM highway format. The i386
works with frequencies from 16 up to more than 50 MHz. If you compare the timing
diagrams you will see that a few glue logic is necessary to adapt the MUNICH32 to the
i386 timing.
A possible adaption of the different frequencies is described below. For an example we
use an i386 with a frequency of 16.384 MHz. The MUNICH32 is configured in the CEPT
32 channel PCM highway format with a SCLK of 16.384 MHz. The SCLK signal is build
by dividing the 32.768 MHz CLK2 signal of the i386. That means that both clocks are
synchronous. This is not necessary in general but selected in our example. The bus
controller generates e.g. one wait state for the memory access. The falling edge of the
ADS signal marks the beginning of a bus cycle which is completed with the sampled
READY signal. A general bus controller should not see a difference between the two bus
masters, so we have to delay the falling edge of the MUNICH32 ADS signal to that
moment as the i386 would generate its ADS to get the READY signal at the same time.
In the picture below you can see the relationship and the adaption of both timings as
specified in our example. A second picture shows the adaption in an i386 24.576 MHz
system. Again the clocks are synchronous.
Application Hints
Frequency Adaption in an Intel 368 Common Bus System
220
Application Hints
PEB 20320
01.2000