pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 158

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
CS:
INV:
CRC:
Receive Frame Examples:
a) 0x7E, data byte, 0x7E
b) 0x7E, data byte = 0xFC (or 0xFD or 0x7F), 0x7E
CRC Select; only used in HDLC mode. Setting this bit to ‘1’ causes the
MUNICH32 to transfer the CRC bits to the data section in the shared memory.
In receive direction the CRC check is carried out whereas in transmit direction
the CRC generation is suppressed, see Chapter 2.4 for more details.
Inversion; If this bit is set, all data of the channel transmitted or received by
the MUNICH32 is inverted.
Cyclic Redundancy Check; in HDLC mode this bit determines the
CRC generator polynomial: When the CRC bit is set to ‘1’ the 32-bit CRC is
performed, otherwise the 16-bit CRC; for TMB/TMR mode this bit
distinguishes:
for all other modes this bit has to be set to ‘0’.
data byte copied to shared memory + frame end
status SF-bit set
no SF indication interrupt generated
FI indication interrupt generated
ERR interrupt generated due to wrong CRC’
no data byte copied to shared memory
SF and FI interrupt generated
TMB: CRC = ‘0’
TMR: CRC = ‘1’
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Detailed Register Description
PEB 20320
01.2000