pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 155

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

– transmit abort
– transmit jump
User’s Manual
TI = 0, TO = 1, TA = 1 (clears receive off condition, sets transmit abort condition,
affects only the serial interface)
This abort is performed in the transmit formatter at the serial interface. The currently
transmitted frame is aborted
by
Afterwards or – if no frame is currently sent directly inter frame time fill:
is sent.
During transmit abort the TF does not access the transmit buffer. The handling of the
link list is not affected by the transmit abort, i.e. the device keeps the TB full. When the
transmit abort is withdrawn the transmit formatter continues the transmission with the
data stored in TB. In the case of HDLC or TMB or TMR mode the remaining data of
the aborted HDLC or TMB frame is sent as a new independent frame. To avoid this
problem the link list must be reinitialized by a transmit initialization command together
with the revoking of the transmission abort.
Another proper use of the transmit abort command consists in setting the last
descriptor of the last frame to be transmitted with HOLD = 1 and waiting for the device
to poll the HOLD bit (ITBS + 2) times where ITBS is the number of long words
assigned to this channel currently. Afterwards TB is empty and the transmit abort then
issued does not abort a currently sent frame. The same procedure can also be used
for the transmit off command.
TI = 1, TO = 0, TA = 0 (clears a transmit off and transmit abort condition, affects only
the DMA interface)
This bit is set only during normal operation. Then MUNICH32 branches to the transmit
descriptor (FTDA) specified in the CCS after finishing the current transmit descriptor
without interrupting or aborting the transmitted frame.
The DMA controller will proceed finishing the current transmit descriptor as usual and
afterwards branch to the new descriptor specified by FTDA. If the current descriptor
does not include a frame end (FE = 0) (HDLC, TMB, TMR) the DMA controller will link
the following data section(s) of the ‘new’ descriptor chain to the opened frame. This
may generate unexpected frames.
011 1111 1111 1111 for HDLC
00
0000
3 frames with erroneous synchronization pattern for V.110/X.30
TFLAG
FF
7E
FF
00
TFLAG
FF
H
H
for TMB
for TMR
for TMA, FA = 1
for TMA, FA = 0.
for HDLC and IFTF = 0
for HDLC and IFTF = 1
for TMB, TMR, V.110/X.30
for TMA, FA = 1
for TMA, FA = 0
155
Detailed Register Description
PEB 20320
01.2000