pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 227

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

6.3.2
A few more effort is necessary to integrate the MUNICH32 into a ST BUS system from
MITEL. The basic assumption made here is that the clock master is the ST BUS system.
That means all signals derived from the ST BUS need to be adapted to match the
MUNICH32 timing requirements. First of all the clock signal C2 must be inverted before
it can be used as the MUNICH32 clocks (TCLK = RCLK = C2). The next step is the
generation of the TSP and RSP pulses out of the F0 signal, which is the ST BUS frame
synchronization signal. The RSP pulse can be derived from the F0 signal by means of a
simple D-Flip-Flop clocked with C2, as depicted in the following Figure 116. Due to the
necessary phase relationship between the serial data streams and their corresponding
TSP, RSP and F0 pulses, the effort to generate the TSP pulse is much higher than for
RSP.
Figure 116
User’s Manual
MUNICH32 in Systems with MITEL ST BUS
MUNICH32
PEB 20320
RDATA
TDATA
RCLK
TCLK
RSP
TSP
Q
Q
Q
Q
STi
STo
227
D
D
C2
System Clock Adaption
ST-BUS
&
F0
Decode
’254’
Counter
RES
8-Bit
Application Hints
PEB 20320
ITS04692
01.2000