pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 144

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
IFC:
SF:
ERR:
always in conjunction with FI = 1
1.1 HDLC mode
1.2 HDLC mode
new frame, or when it starts polling the hold bit if set in conjunction with
the FE bit; ERR and FI are set if a transmit descriptor contains a
HOLD bit no FE bit
Idle/Flag Change; an interrupt is generated in HDLC if the device
changes the interframe time-fill (ITF) state. After reset the device is in the
ITF idle state. It changes to the ITF flag state if it receives 2 consecutive
flags with or without shared zeroes. It changes back to the ITF idle state
upon reception of 15 contiguous ‘1’-bits or when a receive abort channel
command is active during 15 received bits.
Short frame detected
A frame with
has been detected. The sequences 7E 7F
also short frames.
SF is always in conjunction with ERR except for the frames
7E00 007E
7E00 0000 007E
One of the following receive errors occurred
– FCS of the frame was incorrect
– the bit length of the frame was not divisible by 8
– the byte length exceeded MFL
– the frame was stopped by 7F
– the frame could only be partly stored due to
– the frame was ended by a receive abort channel command
– the frame could not be transferred to the shared memory completely
– the frame was aborted by a fast receive abort channel command
A more detailed error analysis can be done by the status information in
the receive descriptor.
one of the following transmit errors occurred:
– the last descriptor had HOLD = 1 and FE = 0
– the last descriptor had NO = 0 and FE = 0
(HDLC mode, receive direction only)
(HDLC mode, receive direction only, always in conjunction with FI)
internal buffer overflow of RB
because of a hold bit set in a receive descriptor not providing enough
bytes for the frame.
H
for CRC16
16 bits between start flag and end flag or end abort flag
32 bits between start flag and end flag or end abort flag
H
for CRC16
for CRC32
for CRC32
Receive Direction
Transmit Direction
144
H
Detailed Register Description
H
and 7E FE
H
and 7E FF
PEB 20320
01.2000
H
are