pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 170

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
BNO:
Status:
HDLC CS = 0
HDLC CS = 1
V.110/X.30
TMB
TMR
TMA
Where ‘0’ means that in the corresponding mode the bit is always ‘0’. It should not be
interpreted though to be upward compatible to future versions.
0
0
7
0
0
0
0
0
• for HDLC, TMB, TMR if the end of a frame was stored in the receive data
• for V.110/X.30 mode if the 3 contiguous frames with errors in the
• for V.110/X.30 mode if the data could not be transferred to the shared
MUNICH32 writes the number of data bytes it has stored in the current data
section into BNO.
The MUNICH32 writes the status information into the status byte whenever it
sets the C-bit. If the status information is not 00 or 40 an interrupt with ERR
bit set is generated. The status is then a means to locate or analyze the
receive error.
The following table gives a general overview over the different status bits in
relation to the channel modes.
section
(interrupt with set FI bit is generated)
synchronization pattern are received
interrupt with set ERR bit
memory due to RB buffer inaccessibility
status = 21 interrupt with set ERR bit.
C indicates that the second long word of the receive descriptor was written
by the MUNICH32. Afterwards the MUNICH32 writes the next receive
descriptor address into CCS. Then it branches to this descriptor
immediately.
SF
6
NI
0
0
0
0
0
FE = 1, status gives the receive status determined by RD
LOSS
0
0
I
0
0
0
5
CRCO
ILN
ILN
0
0
0
0
4
170
NOB
3
IL
IL
0
IL
IL
0
FE = 0, status = 20 or status = 21
Detailed Register Description
LFD
I
I
0
I
I
0
2
FE = 0, status = 01 or
RA
1
I
I
IF
IF
IF
IF
PEB 20320
ROF
01.2000
0
I
I
I
I
I
0