pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 185

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

System Architecture
The system architecture is shown in Figure 88. The MUNICH32, the CPU and the
LAN controller store data in the shared memory. The communication between CPU and
alternate bus master is done via the shared memory. The CPU informs the alternate bus
masters with help of control signals about changes in the shared memory and vice versa.
The MUNICH32 input control signal is the Action Request pulse (ACTION REQUEST).
It is generated by one CPU write cycle to a defined address and decoding the address
lines. The MUNICH32 then responds by generating an interrupt pulse and writing the
respective interrupt information in the SRAM.
Figure 88
System Architecture
User’s Manual
MUNICH32
Control
Signals
Local Bus
CPU
Control
Signals
185
i82596
Shared
Memory
Application Notes
ITS08286
PEB 20320
01.2000