pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 174

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

User’s Manual
5.1.1.2 Internal Channelwise Test Loop
One (and only one) logical channel is mirrored from the serial data output to the serial
data input. The other logical channels are not affected by this operation. The transmit
and receive data rates for this single logical channel must be identical. Normal TCLK,
RCLK, TSP and RSP design rules apply. This test loop provides channelwise testing
capabilities during idle channel time slots, without interfering with normal data
transmission/reception.
Figure 82
5.1.1.3 External Complete Test Loop
The serial data input is physically routed to the serial data output. Data is received on the
RDATA pin and routed to the TDATA pin. The received data can be stored in shared
memory for additional diagnostic purposes. TCLK and RCLK have to be identical; TSP
and RSP have to be identical.
P Interface
CD
Channel X only
1
&
174
Enable Int.
Channelwise Loop
for Channel X
ITS08199
Application Notes
RDATA
TDATA
PEB 20320
01.2000