pef20320 Infineon Technologies Corporation, pef20320 Datasheet - Page 181

• Manufacturer Part Number: pef20320
• Description: Multichannel Network Interface Controller For Hdlc With 32 Channels
• Manufacturer: Infineon Technologies Corporation

Generate AR Pulse and wait for INT signal (set up TS0 and CH0).
Read interrupt queue:
ICQ:
Set ASP for External Channelwise test loop
ASP:
Generate AR Pulse and wait for INT signal.
Read interrupt queue:
ICQ:
Read receive descriptors: ;assumes 64 byte frame externally looped
FRDA:
User’s Manual
9000-8000
9000-1000
9000-1000
A104-0030
9000-8000
9000-0820
9000-1020
0020-0000
4020-0000
RcvDtaPtr
NxtRDPtr
0020-0000
4020-0000
RcvDtaPtr
NxtRDPtr
0020-0000
C000-0000
RcvDtaPtr
NxtRDPtr
4020-0000
0000-0000
RcvDtaPtr
0000-0000
181
;CEPT, MFL=260, Ext. Chnl loop
;Action Request Acknowledge
;V2.2 (V2.1 = 8800-8000)
;Polls HOLD bit of 1st Tx Desc.
;FI Frame indication for the
;Now M32 starts polling HOLD
;Action Request Acknowledge
;Only if other station uses
;Received frame complete
;with proper HDLC framing
;NO = BNO
abcdefghijklmnop
qrstuvwxyz012345
;NO=BNO
ABCDEFGHIJKLMNOP
QRSTUVWXYZ987654
;FE, C = 1, BNO = 0
;empty!
32 byte
data block
1st Tx Desc.
bit of 1st Desc.
idle code 7E
Application Notes
PEB 20320
01.2000