AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 103

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

IEEE 1149.1 (1990) Test Access Port
Interface
An IEEE 1149.1-compatible boundary scan Test Ac-
cess Port is provided for board-level continuity test and
diagnostics. All digital input, output, and input/output
pins are tested. The following paragraphs summarize
the IEEE 1149.1-compatible test functions imple-
mented in the Am79C976 controller.
The boundary scan test circuit requires four pins (TCK,
TMS, TDI and TDO), defined as the Test Access Port
(TAP). It includes a finite state machine (FSM), an in-
8/01/00
BCR Bit Number
Pattern Match
RAM Address
J+m
2+n
0
1
2
J
15
15
39
Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0 Pattern Control End Pattern P
Data Byte 4n+3
Data Byte 3
Data Byte 3
P3 pointer
P7 pointer
PMR_B4
32 31
BCR 47
PMAT1
8
8
Date Byte 4n+2
7
7
Data Byte 2
Data Byte 2
P2 pointer
P6 pointer
PMR_B3
P R E L I M I N A R Y
Pattern Match RAM Bit Number
24
0 15
0 31
Data Byte 4n+1
23
Am79C976
Data Byte 1
P1 pointer
P5 pointer
Data Byte1
PMR_B2
struction register, a data register array. Internal pull-up
resistors are provided for the TDI, TCK, and TMS pins.
The TAP engine is a 16-state finite state machine
(FSM), driven by the Test Clock (TCK), and the Test
Mode Select (TMS) pins. The FSM is reset when TMS
and TDI are high for five TCK periods.
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST, and SAMPLE instructions), three
additional instructions (IDCODE, TRIBYP, and SET-
BYP) are provided to further ease board-level testing.
All unused instruction codes are reserved. See Table
17 for a summary of supported instructions.
24
BCR 46
16
8
Data Byte 4n+0
23
15
7
Data Byte 0
Data Byte 0
P0 pointer
P4 pointer
PMR_B1
PMAT0
7
EOP
16
8
6 5
0
SKIP
7
Pattern Control
Pattern Control End Pattern P
Pattern Control Start Pattern P
Pattern Enable
15
15
PMR_B0
BCR45
4
bits
X
3 2
0
8
8
MASK
1
First Address
Start Pattern
Comments
Address
Second
0
P
1
103
1
k
k