AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 105

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

S_RESET is provided for compatibility with previous
PCnet family devices. S_RESET occurs when the host
CPU reads the Reset register, which is located at offset
14h if the device is operating in Word I/O mode or at off-
set 18h in DWord I/O mode.
S_RESET has the same effect as setting STOP except
that S_RESET resets some Control and Status Regis-
ter (CSR) bits that STOP does not change. See the de-
scriptions of individual Control and Status Registers for
details about which bits are affected. S_RESET does
not trigger an automatic EEPROM read sequence.
New software should not use S_RESET. It should be
replaced by a combination of clearing the RUN bit in
the CMD0 register followed by explicit setting or clear-
ing of control bits as required.
A STOP reset is generated by the assertion of the
STOP bit in CSR0. Writing a 1 to the STOP bit of CSR0,
when the stop bit currently has a value of 0, will initiate
a STOP reset. If the STOP bit is already a 1, then writ-
ing a 1 to the STOP bit will not generate a STOP reset.
STOP will reset all or some portions of CSR0, 3, and 4
to default values. For the identity of individual CSRs
and bit locations that are affected by STOP, see the in-
dividual CSR register descriptions. STOP will not affect
any of the BCR and PCI configuration space locations.
STOP will reset the internal state machines. Following
the end of the STOP operation, the Am79C976 control-
ler will not attempt to read the EEPROM device.
STOP terminates all network activity abruptly. The host
can use the suspend mode (SPND, CSR5, bit 0) to ter-
minate all network activity in an orderly sequence be-
fore setting the STOP bit.
Power on Reset (POR) is generated when the
Am79C976 controller is powered up. POR generates a
hardware reset (H_RESET). In addition, it clears some
bits that H_RESET does not affect.
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P R E L I M I N A R Y
Am79C976
The Am79C976 controller provides the PHY_RST pin
which may be connected to the reset input of an exter-
nal PHY. The polarity of PHY_RST is determined by the
PHY_RST_POL bit in CMD3 (RST_POL in CSR116).
The PHY_RST pin will assert at the start of the read of
the serial EEPROM and will deassert at least 240µs
(the duration of the read of two bytes from the EE-
PROM) before the end of the serial EEPROM read,
providing time for the PHY to recover from the reset.
The PHY_RST_POL bit may be programmed from the
serial EEPROM. The default value is zero, correspond-
ing to an active high PHY_RST signal. If an active low
PHY_RST is required, the CMD3 register should be the
first register programmed from the serial EEPROM.
The duration of the assertion of PHY_RST depends on
the number of registers programmed by the serial
EEPROM. Each register requires at least 240 µs. The
time to program the CMD3 register and any registers
programmed before CMD3 should be ignored in the
c a l c u l a t i o n o f P H Y _ R S T d u r a t i o n i f t h e
PHY_RST_POL bit is programmed to 1.
If the number of registers programmed from the serial
EEPROM results in PHY_RST being too short, the
read-only register at offset 0x28 may be used for pad-
ding. Specify the address as 0x14 with arbitrary data
and repeat as many times as necessary to achieve the
required PHY_RST duration.
If the serial EEPROM is not used, the PHY may be
reset by BIOS or driver software by programming the
correct PHY_RST_POL value, disabling the internal
port manager by setting the DISPM bit, disabling the
auto-poll logic by clearing the APEP bit and then set-
ting the RESET_PHY bit. All these bits are in the CMD3
register.
T h e P H Y _ R S T w i l l b e a s s e r t e d a s l o n g a s
RESET_PHY remains set. If the PHY requires a recov-
ery time after reset, the software must provide the
delay after clearing the RESET_PHY bit before access-
ing the PHY’s registers or enabling the Am79C976 con-
troller's port manager and/or auto-poll logic.
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